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In this paper considers the algorithm of laser beam spots image classification in atmospheric-optical transmission systems. It discusses the need for images filtering using adaptive methods, using, for example, parallel-hierarchic...
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In this paper considers the algorithm of laser beam spots image classification in atmospheric-optical transmission systems. It discusses the need for images filtering using adaptive methods, using, for example, parallel-hierarchical networks. The article also highlights the need to create high-speed memory devices for such networks. Implementation and simulation results of the developed method based on the PLD are demonstrated, which shows that the presented method gives 15-20% better prediction results than similar methods.
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This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded...
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This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.
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The increases for power demand in the Electrical Power System (EPS) causes a significant increase of power in daily load curve and transmission line overload. The large variability in energy consumption in EPS combined with unpred...
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The increases for power demand in the Electrical Power System (EPS) causes a significant increase of power in daily load curve and transmission line overload. The large variability in energy consumption in EPS combined with unpredictable weather events can lead to a situation in which to save the stability of the EPS, the power limits must be introduced or even industrial customers in a given area have to be disconnected, which causes financial losses. Nowadays, a Transmission System Operator is looking for additional solutions to reduce peak power, because existing approaches (mainly building new intervention power unit or tariff programs) are not satisfactory due to the high cost of services in combination with insufficient power reduction effect. The paper presents an approach to load shifting with the use of home Energy Management System (EMS) installed at small end-users. The home energy management algorithm, executed by EMS controller, is modeled using Unified Modeling Language (UML). Then, the UML model is translated into Verilog description, and is finally implemented in the Field Programmable Gate Arrays. The advantages of the proposed approach are the relatively low cost of reduction service, small loss of end-users' comfort, and the convenient maintenance of EMS. A practical example illustrating the proposed approach and calculation of potential gains from its implementation are also presented.
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The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC...
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The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.
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This paper presents a new recursive bipartitioning algorithm for a hierarchical field-programmable system. It draws new insights into relating the quality of the bipartitioning algorithm to circuit structures by the use of the par...
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This paper presents a new recursive bipartitioning algorithm for a hierarchical field-programmable system. It draws new insights into relating the quality of the bipartitioning algorithm to circuit structures by the use of the partitioning tree (Hagen et al., 1994). The final algorithm proposed not only forms the basis for the partitioning solution of a 1-million gate field programmable system (Lewis et al., 1997) but can also be applied to general VLSI or multiple-FPGA partitioning problems.
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FPGA-based processors, like many conventional DSP systems, often associate small high performance memories with each processing chip. These memories may be on-board embedded SRAMs or discrete parts. In the process of mapping a com...
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FPGA-based processors, like many conventional DSP systems, often associate small high performance memories with each processing chip. These memories may be on-board embedded SRAMs or discrete parts. In the process of mapping a computation onto an FPGA processor, it is necessary to map the applications' data to memories. In this work, we present an algorithm that has been implemented in our NAPA C compiler to assign data automatically to memories to produce minimum overall execution time of the loops in the program. With the addition of this algorithm to our compiler, the programmer need not explicitly annotate array declarations with location information. Rather, the compiler analyzes the usage patterns of variables and selects the optimal location for each variable. The algorithm uses a search technique known as implicit enumeration to reduce the otherwise exponential search space. In practice, the use of this memory allocation compiler phase in our SUIF-based NAPA C compiler has negligible effect on compiler run time.
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Providing assurances in newly developed Programmable Electronic Hardware (PEH) used in safety critical system is becoming standard practise following the development of standards such as DO 254. Although these standards mention le...
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Providing assurances in newly developed Programmable Electronic Hardware (PEH) used in safety critical system is becoming standard practise following the development of standards such as DO 254. Although these standards mention legacy PEH, they lack detail on the assurance approaches that should be used. This situation is made more challenging by the fact that often limited developmental evidence is available to form an assurance argument, as the PEH supplier may not have been contractually required to produce such evidence. However, the assurance of legacy PEH needs to be provided due to situations such as systems upgrades. This paper examines the issues of assuring legacy PEH and provides a pragmatic PEH assurance approach. This approach is illustrated in case study of a generic control system that is based on a class of industrial systems.
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Providing assurances in newly developed Programmable Electronic Hardware (PEH) used in safety critical system is becoming standard practise following the development of standards such as DO 254. Although these standards mention le...
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Providing assurances in newly developed Programmable Electronic Hardware (PEH) used in safety critical system is becoming standard practise following the development of standards such as DO 254. Although these standards mention legacy PEH, they lack detail on the assurance approaches that should be used. This situation is made more challenging by the fact that often limited developmental evidence is available to form an assurance argument, as the PEH supplier may not have been contractually required to produce such evidence. However, the assurance of legacy PEH needs to be provided due to situations such as systems upgrades. This paper examines the issues of assuring legacy PEH and provides a pragmatic PEH assurance approach. This approach is illustrated in case study of a generic control system that is based on a class of industrial systems.
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Elevator Group Control Systems (EGCSs) manage multiple elevators in a building transporting efficiently passengers. The performance of an EGCS is measured by means of several metrics such as the average waiting time of passengers,...
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Elevator Group Control Systems (EGCSs) manage multiple elevators in a building transporting efficiently passengers. The performance of an EGCS is measured by means of several metrics such as the average waiting time of passengers, the percentage of the passengers waiting more than some predetermined time, power consumption, among others. Four elevator dispatching algorithms are analyzed and implemented using reconfigurable architectures based on FPGAs. The system is based on Local Controller Systems (LCSs), one for each elevator, and a protocol based on an RS485 network for interconnecting the LCSs. The FPGAs implement the LCSs. A Java interface was implemented for testing and monitoring the system and the EGCS function. The novelty of this approach is that the LCSs are capable to run the different dispatching algorithms, which are suitable for different passenger traffic situations, while the EGCS only must determine the best algorithm to be run in each LCS. The data traffic in the network is reduced given that the EGCS is not directly involved in calculating next floors to be visited. The algorithms were described in VHDL and implemented on Spartan3 FPGA based boards.
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